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<div class="header">
  <div class="headertitle"><div class="title">pio.h</div></div>
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<div class="contents">
<div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno">    1</span><span class="comment">// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT</span></div>
<div class="line"><a id="l00002" name="l00002"></a><span class="lineno">    2</span> </div>
<div class="line"><a id="l00008" name="l00008"></a><span class="lineno">    8</span><span class="preprocessor">#ifndef _HARDWARE_STRUCTS_PIO_H</span></div>
<div class="line"><a id="l00009" name="l00009"></a><span class="lineno">    9</span><span class="preprocessor">#define _HARDWARE_STRUCTS_PIO_H</span></div>
<div class="line"><a id="l00010" name="l00010"></a><span class="lineno">   10</span> </div>
<div class="line"><a id="l00015" name="l00015"></a><span class="lineno">   15</span><span class="preprocessor">#include &quot;<a class="code" href="address__mapped_8h.html">hardware/address_mapped.h</a>&quot;</span></div>
<div class="line"><a id="l00016" name="l00016"></a><span class="lineno">   16</span><span class="preprocessor">#include &quot;hardware/regs/pio.h&quot;</span></div>
<div class="line"><a id="l00017" name="l00017"></a><span class="lineno">   17</span> </div>
<div class="line"><a id="l00018" name="l00018"></a><span class="lineno">   18</span><span class="comment">// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pio</span></div>
<div class="line"><a id="l00019" name="l00019"></a><span class="lineno">   19</span><span class="comment">//</span></div>
<div class="line"><a id="l00020" name="l00020"></a><span class="lineno">   20</span><span class="comment">// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the &quot;Go to Definition&quot; feature)</span></div>
<div class="line"><a id="l00021" name="l00021"></a><span class="lineno">   21</span><span class="comment">// _REG_(x) will link to the corresponding register in hardware/regs/pio.h.</span></div>
<div class="line"><a id="l00022" name="l00022"></a><span class="lineno">   22</span><span class="comment">//</span></div>
<div class="line"><a id="l00023" name="l00023"></a><span class="lineno">   23</span><span class="comment">// Bit-field descriptions are of the form:</span></div>
<div class="line"><a id="l00024" name="l00024"></a><span class="lineno">   24</span><span class="comment">// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION</span></div>
<div class="line"><a id="l00025" name="l00025"></a><span class="lineno">   25</span> </div>
<div class="line"><a id="l00026" name="l00026"></a><span class="lineno">   26</span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00027" name="l00027"></a><span class="lineno">   27</span>    _REG_(PIO_SM0_CLKDIV_OFFSET) <span class="comment">// PIO_SM0_CLKDIV</span></div>
<div class="line"><a id="l00028" name="l00028"></a><span class="lineno">   28</span>    <span class="comment">// Clock divisor register for state machine 0 +</span></div>
<div class="line"><a id="l00029" name="l00029"></a><span class="lineno">   29</span>    <span class="comment">// 0xffff0000 [31:16] INT          (0x0001) Effective frequency is sysclk/(int + frac/256)</span></div>
<div class="line"><a id="l00030" name="l00030"></a><span class="lineno">   30</span>    <span class="comment">// 0x0000ff00 [15:8]  FRAC         (0x00) Fractional part of clock divisor</span></div>
<div class="line"><a id="l00031" name="l00031"></a><span class="lineno">   31</span>    io_rw_32 clkdiv;</div>
<div class="line"><a id="l00032" name="l00032"></a><span class="lineno">   32</span> </div>
<div class="line"><a id="l00033" name="l00033"></a><span class="lineno">   33</span>    _REG_(PIO_SM0_EXECCTRL_OFFSET) <span class="comment">// PIO_SM0_EXECCTRL</span></div>
<div class="line"><a id="l00034" name="l00034"></a><span class="lineno">   34</span>    <span class="comment">// Execution/behavioural settings for state machine 0</span></div>
<div class="line"><a id="l00035" name="l00035"></a><span class="lineno">   35</span>    <span class="comment">// 0x80000000 [31]    EXEC_STALLED (0) If 1, an instruction written to SMx_INSTR is stalled,...</span></div>
<div class="line"><a id="l00036" name="l00036"></a><span class="lineno">   36</span>    <span class="comment">// 0x40000000 [30]    SIDE_EN      (0) If 1, the MSB of the Delay/Side-set instruction field is...</span></div>
<div class="line"><a id="l00037" name="l00037"></a><span class="lineno">   37</span>    <span class="comment">// 0x20000000 [29]    SIDE_PINDIR  (0) If 1, side-set data is asserted to pin directions,...</span></div>
<div class="line"><a id="l00038" name="l00038"></a><span class="lineno">   38</span>    <span class="comment">// 0x1f000000 [28:24] JMP_PIN      (0x00) The GPIO number to use as condition for JMP PIN</span></div>
<div class="line"><a id="l00039" name="l00039"></a><span class="lineno">   39</span>    <span class="comment">// 0x00f80000 [23:19] OUT_EN_SEL   (0x00) Which data bit to use for inline OUT enable</span></div>
<div class="line"><a id="l00040" name="l00040"></a><span class="lineno">   40</span>    <span class="comment">// 0x00040000 [18]    INLINE_OUT_EN (0) If 1, use a bit of OUT data as an auxiliary write enable +</span></div>
<div class="line"><a id="l00041" name="l00041"></a><span class="lineno">   41</span>    <span class="comment">// 0x00020000 [17]    OUT_STICKY   (0) Continuously assert the most recent OUT/SET to the pins</span></div>
<div class="line"><a id="l00042" name="l00042"></a><span class="lineno">   42</span>    <span class="comment">// 0x0001f000 [16:12] WRAP_TOP     (0x1f) After reaching this address, execution is wrapped to wrap_bottom</span></div>
<div class="line"><a id="l00043" name="l00043"></a><span class="lineno">   43</span>    <span class="comment">// 0x00000f80 [11:7]  WRAP_BOTTOM  (0x00) After reaching wrap_top, execution is wrapped to this address</span></div>
<div class="line"><a id="l00044" name="l00044"></a><span class="lineno">   44</span>    <span class="comment">// 0x00000060 [6:5]   STATUS_SEL   (0x0) Comparison used for the MOV x, STATUS instruction</span></div>
<div class="line"><a id="l00045" name="l00045"></a><span class="lineno">   45</span>    <span class="comment">// 0x0000001f [4:0]   STATUS_N     (0x00) Comparison level or IRQ index for the MOV x, STATUS instruction</span></div>
<div class="line"><a id="l00046" name="l00046"></a><span class="lineno">   46</span>    io_rw_32 execctrl;</div>
<div class="line"><a id="l00047" name="l00047"></a><span class="lineno">   47</span> </div>
<div class="line"><a id="l00048" name="l00048"></a><span class="lineno">   48</span>    _REG_(PIO_SM0_SHIFTCTRL_OFFSET) <span class="comment">// PIO_SM0_SHIFTCTRL</span></div>
<div class="line"><a id="l00049" name="l00049"></a><span class="lineno">   49</span>    <span class="comment">// Control behaviour of the input/output shift registers for state machine 0</span></div>
<div class="line"><a id="l00050" name="l00050"></a><span class="lineno">   50</span>    <span class="comment">// 0x80000000 [31]    FJOIN_RX     (0) When 1, RX FIFO steals the TX FIFO&#39;s storage, and...</span></div>
<div class="line"><a id="l00051" name="l00051"></a><span class="lineno">   51</span>    <span class="comment">// 0x40000000 [30]    FJOIN_TX     (0) When 1, TX FIFO steals the RX FIFO&#39;s storage, and...</span></div>
<div class="line"><a id="l00052" name="l00052"></a><span class="lineno">   52</span>    <span class="comment">// 0x3e000000 [29:25] PULL_THRESH  (0x00) Number of bits shifted out of OSR before autopull, or...</span></div>
<div class="line"><a id="l00053" name="l00053"></a><span class="lineno">   53</span>    <span class="comment">// 0x01f00000 [24:20] PUSH_THRESH  (0x00) Number of bits shifted into ISR before autopush, or...</span></div>
<div class="line"><a id="l00054" name="l00054"></a><span class="lineno">   54</span>    <span class="comment">// 0x00080000 [19]    OUT_SHIFTDIR (1) 1 = shift out of output shift register to right</span></div>
<div class="line"><a id="l00055" name="l00055"></a><span class="lineno">   55</span>    <span class="comment">// 0x00040000 [18]    IN_SHIFTDIR  (1) 1 = shift input shift register to right (data enters from left)</span></div>
<div class="line"><a id="l00056" name="l00056"></a><span class="lineno">   56</span>    <span class="comment">// 0x00020000 [17]    AUTOPULL     (0) Pull automatically when the output shift register is emptied, i</span></div>
<div class="line"><a id="l00057" name="l00057"></a><span class="lineno">   57</span>    <span class="comment">// 0x00010000 [16]    AUTOPUSH     (0) Push automatically when the input shift register is filled, i</span></div>
<div class="line"><a id="l00058" name="l00058"></a><span class="lineno">   58</span>    <span class="comment">// 0x00008000 [15]    FJOIN_RX_PUT (0) If 1, disable this state machine&#39;s RX FIFO, make its...</span></div>
<div class="line"><a id="l00059" name="l00059"></a><span class="lineno">   59</span>    <span class="comment">// 0x00004000 [14]    FJOIN_RX_GET (0) If 1, disable this state machine&#39;s RX FIFO, make its...</span></div>
<div class="line"><a id="l00060" name="l00060"></a><span class="lineno">   60</span>    <span class="comment">// 0x0000001f [4:0]   IN_COUNT     (0x00) Set the number of pins which are not masked to 0 when...</span></div>
<div class="line"><a id="l00061" name="l00061"></a><span class="lineno">   61</span>    io_rw_32 shiftctrl;</div>
<div class="line"><a id="l00062" name="l00062"></a><span class="lineno">   62</span> </div>
<div class="line"><a id="l00063" name="l00063"></a><span class="lineno">   63</span>    _REG_(PIO_SM0_ADDR_OFFSET) <span class="comment">// PIO_SM0_ADDR</span></div>
<div class="line"><a id="l00064" name="l00064"></a><span class="lineno">   64</span>    <span class="comment">// Current instruction address of state machine 0</span></div>
<div class="line"><a id="l00065" name="l00065"></a><span class="lineno">   65</span>    <span class="comment">// 0x0000001f [4:0]   SM0_ADDR     (0x00) </span></div>
<div class="line"><a id="l00066" name="l00066"></a><span class="lineno">   66</span>    io_ro_32 addr;</div>
<div class="line"><a id="l00067" name="l00067"></a><span class="lineno">   67</span> </div>
<div class="line"><a id="l00068" name="l00068"></a><span class="lineno">   68</span>    _REG_(PIO_SM0_INSTR_OFFSET) <span class="comment">// PIO_SM0_INSTR</span></div>
<div class="line"><a id="l00069" name="l00069"></a><span class="lineno">   69</span>    <span class="comment">// Read to see the instruction currently addressed by state machine 0&#39;s program counter +</span></div>
<div class="line"><a id="l00070" name="l00070"></a><span class="lineno">   70</span>    <span class="comment">// 0x0000ffff [15:0]  SM0_INSTR    (-) </span></div>
<div class="line"><a id="l00071" name="l00071"></a><span class="lineno">   71</span>    io_rw_32 instr;</div>
<div class="line"><a id="l00072" name="l00072"></a><span class="lineno">   72</span> </div>
<div class="line"><a id="l00073" name="l00073"></a><span class="lineno">   73</span>    _REG_(PIO_SM0_PINCTRL_OFFSET) <span class="comment">// PIO_SM0_PINCTRL</span></div>
<div class="line"><a id="l00074" name="l00074"></a><span class="lineno">   74</span>    <span class="comment">// State machine pin control</span></div>
<div class="line"><a id="l00075" name="l00075"></a><span class="lineno">   75</span>    <span class="comment">// 0xe0000000 [31:29] SIDESET_COUNT (0x0) The number of MSBs of the Delay/Side-set instruction...</span></div>
<div class="line"><a id="l00076" name="l00076"></a><span class="lineno">   76</span>    <span class="comment">// 0x1c000000 [28:26] SET_COUNT    (0x5) The number of pins asserted by a SET</span></div>
<div class="line"><a id="l00077" name="l00077"></a><span class="lineno">   77</span>    <span class="comment">// 0x03f00000 [25:20] OUT_COUNT    (0x00) The number of pins asserted by an OUT PINS, OUT PINDIRS...</span></div>
<div class="line"><a id="l00078" name="l00078"></a><span class="lineno">   78</span>    <span class="comment">// 0x000f8000 [19:15] IN_BASE      (0x00) The pin which is mapped to the least-significant bit of...</span></div>
<div class="line"><a id="l00079" name="l00079"></a><span class="lineno">   79</span>    <span class="comment">// 0x00007c00 [14:10] SIDESET_BASE (0x00) The lowest-numbered pin that will be affected by a...</span></div>
<div class="line"><a id="l00080" name="l00080"></a><span class="lineno">   80</span>    <span class="comment">// 0x000003e0 [9:5]   SET_BASE     (0x00) The lowest-numbered pin that will be affected by a SET...</span></div>
<div class="line"><a id="l00081" name="l00081"></a><span class="lineno">   81</span>    <span class="comment">// 0x0000001f [4:0]   OUT_BASE     (0x00) The lowest-numbered pin that will be affected by an OUT...</span></div>
<div class="line"><a id="l00082" name="l00082"></a><span class="lineno">   82</span>    io_rw_32 pinctrl;</div>
<div class="line"><a id="l00083" name="l00083"></a><span class="lineno">   83</span>} <a class="code hl_struct" href="structpio__sm__hw__t.html">pio_sm_hw_t</a>;</div>
<div class="line"><a id="l00084" name="l00084"></a><span class="lineno">   84</span> </div>
<div class="line"><a id="l00085" name="l00085"></a><span class="lineno">   85</span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00086" name="l00086"></a><span class="lineno">   86</span>    _REG_(PIO_IRQ0_INTE_OFFSET) <span class="comment">// PIO_IRQ0_INTE</span></div>
<div class="line"><a id="l00087" name="l00087"></a><span class="lineno">   87</span>    <span class="comment">// Interrupt Enable for irq0</span></div>
<div class="line"><a id="l00088" name="l00088"></a><span class="lineno">   88</span>    <span class="comment">// 0x00008000 [15]    SM7          (0) </span></div>
<div class="line"><a id="l00089" name="l00089"></a><span class="lineno">   89</span>    <span class="comment">// 0x00004000 [14]    SM6          (0) </span></div>
<div class="line"><a id="l00090" name="l00090"></a><span class="lineno">   90</span>    <span class="comment">// 0x00002000 [13]    SM5          (0) </span></div>
<div class="line"><a id="l00091" name="l00091"></a><span class="lineno">   91</span>    <span class="comment">// 0x00001000 [12]    SM4          (0) </span></div>
<div class="line"><a id="l00092" name="l00092"></a><span class="lineno">   92</span>    <span class="comment">// 0x00000800 [11]    SM3          (0) </span></div>
<div class="line"><a id="l00093" name="l00093"></a><span class="lineno">   93</span>    <span class="comment">// 0x00000400 [10]    SM2          (0) </span></div>
<div class="line"><a id="l00094" name="l00094"></a><span class="lineno">   94</span>    <span class="comment">// 0x00000200 [9]     SM1          (0) </span></div>
<div class="line"><a id="l00095" name="l00095"></a><span class="lineno">   95</span>    <span class="comment">// 0x00000100 [8]     SM0          (0) </span></div>
<div class="line"><a id="l00096" name="l00096"></a><span class="lineno">   96</span>    <span class="comment">// 0x00000080 [7]     SM3_TXNFULL  (0) </span></div>
<div class="line"><a id="l00097" name="l00097"></a><span class="lineno">   97</span>    <span class="comment">// 0x00000040 [6]     SM2_TXNFULL  (0) </span></div>
<div class="line"><a id="l00098" name="l00098"></a><span class="lineno">   98</span>    <span class="comment">// 0x00000020 [5]     SM1_TXNFULL  (0) </span></div>
<div class="line"><a id="l00099" name="l00099"></a><span class="lineno">   99</span>    <span class="comment">// 0x00000010 [4]     SM0_TXNFULL  (0) </span></div>
<div class="line"><a id="l00100" name="l00100"></a><span class="lineno">  100</span>    <span class="comment">// 0x00000008 [3]     SM3_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00101" name="l00101"></a><span class="lineno">  101</span>    <span class="comment">// 0x00000004 [2]     SM2_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00102" name="l00102"></a><span class="lineno">  102</span>    <span class="comment">// 0x00000002 [1]     SM1_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00103" name="l00103"></a><span class="lineno">  103</span>    <span class="comment">// 0x00000001 [0]     SM0_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00104" name="l00104"></a><span class="lineno">  104</span>    io_rw_32 inte;</div>
<div class="line"><a id="l00105" name="l00105"></a><span class="lineno">  105</span> </div>
<div class="line"><a id="l00106" name="l00106"></a><span class="lineno">  106</span>    _REG_(PIO_IRQ0_INTF_OFFSET) <span class="comment">// PIO_IRQ0_INTF</span></div>
<div class="line"><a id="l00107" name="l00107"></a><span class="lineno">  107</span>    <span class="comment">// Interrupt Force for irq0</span></div>
<div class="line"><a id="l00108" name="l00108"></a><span class="lineno">  108</span>    <span class="comment">// 0x00008000 [15]    SM7          (0) </span></div>
<div class="line"><a id="l00109" name="l00109"></a><span class="lineno">  109</span>    <span class="comment">// 0x00004000 [14]    SM6          (0) </span></div>
<div class="line"><a id="l00110" name="l00110"></a><span class="lineno">  110</span>    <span class="comment">// 0x00002000 [13]    SM5          (0) </span></div>
<div class="line"><a id="l00111" name="l00111"></a><span class="lineno">  111</span>    <span class="comment">// 0x00001000 [12]    SM4          (0) </span></div>
<div class="line"><a id="l00112" name="l00112"></a><span class="lineno">  112</span>    <span class="comment">// 0x00000800 [11]    SM3          (0) </span></div>
<div class="line"><a id="l00113" name="l00113"></a><span class="lineno">  113</span>    <span class="comment">// 0x00000400 [10]    SM2          (0) </span></div>
<div class="line"><a id="l00114" name="l00114"></a><span class="lineno">  114</span>    <span class="comment">// 0x00000200 [9]     SM1          (0) </span></div>
<div class="line"><a id="l00115" name="l00115"></a><span class="lineno">  115</span>    <span class="comment">// 0x00000100 [8]     SM0          (0) </span></div>
<div class="line"><a id="l00116" name="l00116"></a><span class="lineno">  116</span>    <span class="comment">// 0x00000080 [7]     SM3_TXNFULL  (0) </span></div>
<div class="line"><a id="l00117" name="l00117"></a><span class="lineno">  117</span>    <span class="comment">// 0x00000040 [6]     SM2_TXNFULL  (0) </span></div>
<div class="line"><a id="l00118" name="l00118"></a><span class="lineno">  118</span>    <span class="comment">// 0x00000020 [5]     SM1_TXNFULL  (0) </span></div>
<div class="line"><a id="l00119" name="l00119"></a><span class="lineno">  119</span>    <span class="comment">// 0x00000010 [4]     SM0_TXNFULL  (0) </span></div>
<div class="line"><a id="l00120" name="l00120"></a><span class="lineno">  120</span>    <span class="comment">// 0x00000008 [3]     SM3_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00121" name="l00121"></a><span class="lineno">  121</span>    <span class="comment">// 0x00000004 [2]     SM2_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00122" name="l00122"></a><span class="lineno">  122</span>    <span class="comment">// 0x00000002 [1]     SM1_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00123" name="l00123"></a><span class="lineno">  123</span>    <span class="comment">// 0x00000001 [0]     SM0_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00124" name="l00124"></a><span class="lineno">  124</span>    io_rw_32 intf;</div>
<div class="line"><a id="l00125" name="l00125"></a><span class="lineno">  125</span> </div>
<div class="line"><a id="l00126" name="l00126"></a><span class="lineno">  126</span>    _REG_(PIO_IRQ0_INTS_OFFSET) <span class="comment">// PIO_IRQ0_INTS</span></div>
<div class="line"><a id="l00127" name="l00127"></a><span class="lineno">  127</span>    <span class="comment">// Interrupt status after masking &amp; forcing for irq0</span></div>
<div class="line"><a id="l00128" name="l00128"></a><span class="lineno">  128</span>    <span class="comment">// 0x00008000 [15]    SM7          (0) </span></div>
<div class="line"><a id="l00129" name="l00129"></a><span class="lineno">  129</span>    <span class="comment">// 0x00004000 [14]    SM6          (0) </span></div>
<div class="line"><a id="l00130" name="l00130"></a><span class="lineno">  130</span>    <span class="comment">// 0x00002000 [13]    SM5          (0) </span></div>
<div class="line"><a id="l00131" name="l00131"></a><span class="lineno">  131</span>    <span class="comment">// 0x00001000 [12]    SM4          (0) </span></div>
<div class="line"><a id="l00132" name="l00132"></a><span class="lineno">  132</span>    <span class="comment">// 0x00000800 [11]    SM3          (0) </span></div>
<div class="line"><a id="l00133" name="l00133"></a><span class="lineno">  133</span>    <span class="comment">// 0x00000400 [10]    SM2          (0) </span></div>
<div class="line"><a id="l00134" name="l00134"></a><span class="lineno">  134</span>    <span class="comment">// 0x00000200 [9]     SM1          (0) </span></div>
<div class="line"><a id="l00135" name="l00135"></a><span class="lineno">  135</span>    <span class="comment">// 0x00000100 [8]     SM0          (0) </span></div>
<div class="line"><a id="l00136" name="l00136"></a><span class="lineno">  136</span>    <span class="comment">// 0x00000080 [7]     SM3_TXNFULL  (0) </span></div>
<div class="line"><a id="l00137" name="l00137"></a><span class="lineno">  137</span>    <span class="comment">// 0x00000040 [6]     SM2_TXNFULL  (0) </span></div>
<div class="line"><a id="l00138" name="l00138"></a><span class="lineno">  138</span>    <span class="comment">// 0x00000020 [5]     SM1_TXNFULL  (0) </span></div>
<div class="line"><a id="l00139" name="l00139"></a><span class="lineno">  139</span>    <span class="comment">// 0x00000010 [4]     SM0_TXNFULL  (0) </span></div>
<div class="line"><a id="l00140" name="l00140"></a><span class="lineno">  140</span>    <span class="comment">// 0x00000008 [3]     SM3_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00141" name="l00141"></a><span class="lineno">  141</span>    <span class="comment">// 0x00000004 [2]     SM2_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00142" name="l00142"></a><span class="lineno">  142</span>    <span class="comment">// 0x00000002 [1]     SM1_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00143" name="l00143"></a><span class="lineno">  143</span>    <span class="comment">// 0x00000001 [0]     SM0_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00144" name="l00144"></a><span class="lineno">  144</span>    io_ro_32 ints;</div>
<div class="line"><a id="l00145" name="l00145"></a><span class="lineno">  145</span>} <a class="code hl_struct" href="structpio__irq__ctrl__hw__t.html">pio_irq_ctrl_hw_t</a>;</div>
<div class="line"><a id="l00146" name="l00146"></a><span class="lineno">  146</span> </div>
<div class="line"><a id="l00147" name="l00147"></a><span class="lineno">  147</span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00148" name="l00148"></a><span class="lineno">  148</span>    _REG_(PIO_CTRL_OFFSET) <span class="comment">// PIO_CTRL</span></div>
<div class="line"><a id="l00149" name="l00149"></a><span class="lineno">  149</span>    <span class="comment">// PIO control register</span></div>
<div class="line"><a id="l00150" name="l00150"></a><span class="lineno">  150</span>    <span class="comment">// 0x04000000 [26]    NEXTPREV_CLKDIV_RESTART (0) Write 1 to restart the clock dividers of state machines...</span></div>
<div class="line"><a id="l00151" name="l00151"></a><span class="lineno">  151</span>    <span class="comment">// 0x02000000 [25]    NEXTPREV_SM_DISABLE (0) Write 1 to disable state machines in neighbouring PIO...</span></div>
<div class="line"><a id="l00152" name="l00152"></a><span class="lineno">  152</span>    <span class="comment">// 0x01000000 [24]    NEXTPREV_SM_ENABLE (0) Write 1 to enable state machines in neighbouring PIO...</span></div>
<div class="line"><a id="l00153" name="l00153"></a><span class="lineno">  153</span>    <span class="comment">// 0x00f00000 [23:20] NEXT_PIO_MASK (0x0) A mask of state machines in the neighbouring...</span></div>
<div class="line"><a id="l00154" name="l00154"></a><span class="lineno">  154</span>    <span class="comment">// 0x000f0000 [19:16] PREV_PIO_MASK (0x0) A mask of state machines in the neighbouring...</span></div>
<div class="line"><a id="l00155" name="l00155"></a><span class="lineno">  155</span>    <span class="comment">// 0x00000f00 [11:8]  CLKDIV_RESTART (0x0) Restart a state machine&#39;s clock divider from an initial...</span></div>
<div class="line"><a id="l00156" name="l00156"></a><span class="lineno">  156</span>    <span class="comment">// 0x000000f0 [7:4]   SM_RESTART   (0x0) Write 1 to instantly clear internal SM state which may...</span></div>
<div class="line"><a id="l00157" name="l00157"></a><span class="lineno">  157</span>    <span class="comment">// 0x0000000f [3:0]   SM_ENABLE    (0x0) Enable/disable each of the four state machines by...</span></div>
<div class="line"><a id="l00158" name="l00158"></a><span class="lineno">  158</span>    io_rw_32 ctrl;</div>
<div class="line"><a id="l00159" name="l00159"></a><span class="lineno">  159</span> </div>
<div class="line"><a id="l00160" name="l00160"></a><span class="lineno">  160</span>    _REG_(PIO_FSTAT_OFFSET) <span class="comment">// PIO_FSTAT</span></div>
<div class="line"><a id="l00161" name="l00161"></a><span class="lineno">  161</span>    <span class="comment">// FIFO status register</span></div>
<div class="line"><a id="l00162" name="l00162"></a><span class="lineno">  162</span>    <span class="comment">// 0x0f000000 [27:24] TXEMPTY      (0xf) State machine TX FIFO is empty</span></div>
<div class="line"><a id="l00163" name="l00163"></a><span class="lineno">  163</span>    <span class="comment">// 0x000f0000 [19:16] TXFULL       (0x0) State machine TX FIFO is full</span></div>
<div class="line"><a id="l00164" name="l00164"></a><span class="lineno">  164</span>    <span class="comment">// 0x00000f00 [11:8]  RXEMPTY      (0xf) State machine RX FIFO is empty</span></div>
<div class="line"><a id="l00165" name="l00165"></a><span class="lineno">  165</span>    <span class="comment">// 0x0000000f [3:0]   RXFULL       (0x0) State machine RX FIFO is full</span></div>
<div class="line"><a id="l00166" name="l00166"></a><span class="lineno">  166</span>    io_ro_32 fstat;</div>
<div class="line"><a id="l00167" name="l00167"></a><span class="lineno">  167</span> </div>
<div class="line"><a id="l00168" name="l00168"></a><span class="lineno">  168</span>    _REG_(PIO_FDEBUG_OFFSET) <span class="comment">// PIO_FDEBUG</span></div>
<div class="line"><a id="l00169" name="l00169"></a><span class="lineno">  169</span>    <span class="comment">// FIFO debug register</span></div>
<div class="line"><a id="l00170" name="l00170"></a><span class="lineno">  170</span>    <span class="comment">// 0x0f000000 [27:24] TXSTALL      (0x0) State machine has stalled on empty TX FIFO during a...</span></div>
<div class="line"><a id="l00171" name="l00171"></a><span class="lineno">  171</span>    <span class="comment">// 0x000f0000 [19:16] TXOVER       (0x0) TX FIFO overflow (i</span></div>
<div class="line"><a id="l00172" name="l00172"></a><span class="lineno">  172</span>    <span class="comment">// 0x00000f00 [11:8]  RXUNDER      (0x0) RX FIFO underflow (i</span></div>
<div class="line"><a id="l00173" name="l00173"></a><span class="lineno">  173</span>    <span class="comment">// 0x0000000f [3:0]   RXSTALL      (0x0) State machine has stalled on full RX FIFO during a...</span></div>
<div class="line"><a id="l00174" name="l00174"></a><span class="lineno">  174</span>    io_rw_32 fdebug;</div>
<div class="line"><a id="l00175" name="l00175"></a><span class="lineno">  175</span> </div>
<div class="line"><a id="l00176" name="l00176"></a><span class="lineno">  176</span>    _REG_(PIO_FLEVEL_OFFSET) <span class="comment">// PIO_FLEVEL</span></div>
<div class="line"><a id="l00177" name="l00177"></a><span class="lineno">  177</span>    <span class="comment">// FIFO levels</span></div>
<div class="line"><a id="l00178" name="l00178"></a><span class="lineno">  178</span>    <span class="comment">// 0xf0000000 [31:28] RX3          (0x0) </span></div>
<div class="line"><a id="l00179" name="l00179"></a><span class="lineno">  179</span>    <span class="comment">// 0x0f000000 [27:24] TX3          (0x0) </span></div>
<div class="line"><a id="l00180" name="l00180"></a><span class="lineno">  180</span>    <span class="comment">// 0x00f00000 [23:20] RX2          (0x0) </span></div>
<div class="line"><a id="l00181" name="l00181"></a><span class="lineno">  181</span>    <span class="comment">// 0x000f0000 [19:16] TX2          (0x0) </span></div>
<div class="line"><a id="l00182" name="l00182"></a><span class="lineno">  182</span>    <span class="comment">// 0x0000f000 [15:12] RX1          (0x0) </span></div>
<div class="line"><a id="l00183" name="l00183"></a><span class="lineno">  183</span>    <span class="comment">// 0x00000f00 [11:8]  TX1          (0x0) </span></div>
<div class="line"><a id="l00184" name="l00184"></a><span class="lineno">  184</span>    <span class="comment">// 0x000000f0 [7:4]   RX0          (0x0) </span></div>
<div class="line"><a id="l00185" name="l00185"></a><span class="lineno">  185</span>    <span class="comment">// 0x0000000f [3:0]   TX0          (0x0) </span></div>
<div class="line"><a id="l00186" name="l00186"></a><span class="lineno">  186</span>    io_ro_32 flevel;</div>
<div class="line"><a id="l00187" name="l00187"></a><span class="lineno">  187</span> </div>
<div class="line"><a id="l00188" name="l00188"></a><span class="lineno">  188</span>    <span class="comment">// (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00189" name="l00189"></a><span class="lineno">  189</span>    _REG_(PIO_TXF0_OFFSET) <span class="comment">// PIO_TXF0</span></div>
<div class="line"><a id="l00190" name="l00190"></a><span class="lineno">  190</span>    <span class="comment">// Direct write access to the TX FIFO for this state machine</span></div>
<div class="line"><a id="l00191" name="l00191"></a><span class="lineno">  191</span>    <span class="comment">// 0xffffffff [31:0]  TXF0         (0x00000000) </span></div>
<div class="line"><a id="l00192" name="l00192"></a><span class="lineno">  192</span>    io_wo_32 txf[4];</div>
<div class="line"><a id="l00193" name="l00193"></a><span class="lineno">  193</span> </div>
<div class="line"><a id="l00194" name="l00194"></a><span class="lineno">  194</span>    <span class="comment">// (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00195" name="l00195"></a><span class="lineno">  195</span>    _REG_(PIO_RXF0_OFFSET) <span class="comment">// PIO_RXF0</span></div>
<div class="line"><a id="l00196" name="l00196"></a><span class="lineno">  196</span>    <span class="comment">// Direct read access to the RX FIFO for this state machine</span></div>
<div class="line"><a id="l00197" name="l00197"></a><span class="lineno">  197</span>    <span class="comment">// 0xffffffff [31:0]  RXF0         (-) </span></div>
<div class="line"><a id="l00198" name="l00198"></a><span class="lineno">  198</span>    io_ro_32 rxf[4];</div>
<div class="line"><a id="l00199" name="l00199"></a><span class="lineno">  199</span> </div>
<div class="line"><a id="l00200" name="l00200"></a><span class="lineno">  200</span>    _REG_(PIO_IRQ_OFFSET) <span class="comment">// PIO_IRQ</span></div>
<div class="line"><a id="l00201" name="l00201"></a><span class="lineno">  201</span>    <span class="comment">// State machine IRQ flags register</span></div>
<div class="line"><a id="l00202" name="l00202"></a><span class="lineno">  202</span>    <span class="comment">// 0x000000ff [7:0]   IRQ          (0x00) </span></div>
<div class="line"><a id="l00203" name="l00203"></a><span class="lineno">  203</span>    io_rw_32 irq;</div>
<div class="line"><a id="l00204" name="l00204"></a><span class="lineno">  204</span> </div>
<div class="line"><a id="l00205" name="l00205"></a><span class="lineno">  205</span>    _REG_(PIO_IRQ_FORCE_OFFSET) <span class="comment">// PIO_IRQ_FORCE</span></div>
<div class="line"><a id="l00206" name="l00206"></a><span class="lineno">  206</span>    <span class="comment">// Writing a 1 to each of these bits will forcibly assert the corresponding IRQ</span></div>
<div class="line"><a id="l00207" name="l00207"></a><span class="lineno">  207</span>    <span class="comment">// 0x000000ff [7:0]   IRQ_FORCE    (0x00) </span></div>
<div class="line"><a id="l00208" name="l00208"></a><span class="lineno">  208</span>    io_wo_32 irq_force;</div>
<div class="line"><a id="l00209" name="l00209"></a><span class="lineno">  209</span> </div>
<div class="line"><a id="l00210" name="l00210"></a><span class="lineno">  210</span>    _REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) <span class="comment">// PIO_INPUT_SYNC_BYPASS</span></div>
<div class="line"><a id="l00211" name="l00211"></a><span class="lineno">  211</span>    <span class="comment">// There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities</span></div>
<div class="line"><a id="l00212" name="l00212"></a><span class="lineno">  212</span>    <span class="comment">// 0xffffffff [31:0]  INPUT_SYNC_BYPASS (0x00000000) </span></div>
<div class="line"><a id="l00213" name="l00213"></a><span class="lineno">  213</span>    io_rw_32 input_sync_bypass;</div>
<div class="line"><a id="l00214" name="l00214"></a><span class="lineno">  214</span> </div>
<div class="line"><a id="l00215" name="l00215"></a><span class="lineno">  215</span>    _REG_(PIO_DBG_PADOUT_OFFSET) <span class="comment">// PIO_DBG_PADOUT</span></div>
<div class="line"><a id="l00216" name="l00216"></a><span class="lineno">  216</span>    <span class="comment">// Read to sample the pad output values PIO is currently driving to the GPIOs</span></div>
<div class="line"><a id="l00217" name="l00217"></a><span class="lineno">  217</span>    <span class="comment">// 0xffffffff [31:0]  DBG_PADOUT   (0x00000000) </span></div>
<div class="line"><a id="l00218" name="l00218"></a><span class="lineno">  218</span>    io_ro_32 dbg_padout;</div>
<div class="line"><a id="l00219" name="l00219"></a><span class="lineno">  219</span> </div>
<div class="line"><a id="l00220" name="l00220"></a><span class="lineno">  220</span>    _REG_(PIO_DBG_PADOE_OFFSET) <span class="comment">// PIO_DBG_PADOE</span></div>
<div class="line"><a id="l00221" name="l00221"></a><span class="lineno">  221</span>    <span class="comment">// Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs</span></div>
<div class="line"><a id="l00222" name="l00222"></a><span class="lineno">  222</span>    <span class="comment">// 0xffffffff [31:0]  DBG_PADOE    (0x00000000) </span></div>
<div class="line"><a id="l00223" name="l00223"></a><span class="lineno">  223</span>    io_ro_32 dbg_padoe;</div>
<div class="line"><a id="l00224" name="l00224"></a><span class="lineno">  224</span> </div>
<div class="line"><a id="l00225" name="l00225"></a><span class="lineno">  225</span>    _REG_(PIO_DBG_CFGINFO_OFFSET) <span class="comment">// PIO_DBG_CFGINFO</span></div>
<div class="line"><a id="l00226" name="l00226"></a><span class="lineno">  226</span>    <span class="comment">// The PIO hardware has some free parameters that may vary between chip products</span></div>
<div class="line"><a id="l00227" name="l00227"></a><span class="lineno">  227</span>    <span class="comment">// 0xf0000000 [31:28] VERSION      (0x1) Version of the core PIO hardware</span></div>
<div class="line"><a id="l00228" name="l00228"></a><span class="lineno">  228</span>    <span class="comment">// 0x003f0000 [21:16] IMEM_SIZE    (-) The size of the instruction memory, measured in units of...</span></div>
<div class="line"><a id="l00229" name="l00229"></a><span class="lineno">  229</span>    <span class="comment">// 0x00000f00 [11:8]  SM_COUNT     (-) The number of state machines this PIO instance is equipped with</span></div>
<div class="line"><a id="l00230" name="l00230"></a><span class="lineno">  230</span>    <span class="comment">// 0x0000003f [5:0]   FIFO_DEPTH   (-) The depth of the state machine TX/RX FIFOs, measured in words</span></div>
<div class="line"><a id="l00231" name="l00231"></a><span class="lineno">  231</span>    io_ro_32 dbg_cfginfo;</div>
<div class="line"><a id="l00232" name="l00232"></a><span class="lineno">  232</span> </div>
<div class="line"><a id="l00233" name="l00233"></a><span class="lineno">  233</span>    <span class="comment">// (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00234" name="l00234"></a><span class="lineno">  234</span>    _REG_(PIO_INSTR_MEM0_OFFSET) <span class="comment">// PIO_INSTR_MEM0</span></div>
<div class="line"><a id="l00235" name="l00235"></a><span class="lineno">  235</span>    <span class="comment">// Write-only access to instruction memory location 0</span></div>
<div class="line"><a id="l00236" name="l00236"></a><span class="lineno">  236</span>    <span class="comment">// 0x0000ffff [15:0]  INSTR_MEM0   (0x0000) </span></div>
<div class="line"><a id="l00237" name="l00237"></a><span class="lineno">  237</span>    io_wo_32 instr_mem[32];</div>
<div class="line"><a id="l00238" name="l00238"></a><span class="lineno">  238</span> </div>
<div class="line"><a id="l00239" name="l00239"></a><span class="lineno">  239</span>    <a class="code hl_struct" href="structpio__sm__hw__t.html">pio_sm_hw_t</a> sm[4];</div>
<div class="line"><a id="l00240" name="l00240"></a><span class="lineno">  240</span> </div>
<div class="line"><a id="l00241" name="l00241"></a><span class="lineno">  241</span>    <span class="comment">// (Description copied from array index 0 register PIO_RXF0_PUTGET0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00242" name="l00242"></a><span class="lineno">  242</span>    _REG_(PIO_RXF0_PUTGET0_OFFSET) <span class="comment">// PIO_RXF0_PUTGET0</span></div>
<div class="line"><a id="l00243" name="l00243"></a><span class="lineno">  243</span>    <span class="comment">// Direct read/write access to the RX FIFO on all SMs, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set</span></div>
<div class="line"><a id="l00244" name="l00244"></a><span class="lineno">  244</span>    <span class="comment">// 0xffffffff [31:0]  RXF0_PUTGET0 (0x00000000) </span></div>
<div class="line"><a id="l00245" name="l00245"></a><span class="lineno">  245</span>    io_rw_32 rxf_putget[4][4];</div>
<div class="line"><a id="l00246" name="l00246"></a><span class="lineno">  246</span> </div>
<div class="line"><a id="l00247" name="l00247"></a><span class="lineno">  247</span>    _REG_(PIO_GPIOBASE_OFFSET) <span class="comment">// PIO_GPIOBASE</span></div>
<div class="line"><a id="l00248" name="l00248"></a><span class="lineno">  248</span>    <span class="comment">// Relocate GPIO 0 (from PIO&#39;s point of view) in the system GPIO numbering, to access more than 32...</span></div>
<div class="line"><a id="l00249" name="l00249"></a><span class="lineno">  249</span>    <span class="comment">// 0x00000010 [4]     GPIOBASE     (0) </span></div>
<div class="line"><a id="l00250" name="l00250"></a><span class="lineno">  250</span>    io_rw_32 gpiobase;</div>
<div class="line"><a id="l00251" name="l00251"></a><span class="lineno">  251</span> </div>
<div class="line"><a id="l00252" name="l00252"></a><span class="lineno">  252</span>    _REG_(PIO_INTR_OFFSET) <span class="comment">// PIO_INTR</span></div>
<div class="line"><a id="l00253" name="l00253"></a><span class="lineno">  253</span>    <span class="comment">// Raw Interrupts</span></div>
<div class="line"><a id="l00254" name="l00254"></a><span class="lineno">  254</span>    <span class="comment">// 0x00008000 [15]    SM7          (0) </span></div>
<div class="line"><a id="l00255" name="l00255"></a><span class="lineno">  255</span>    <span class="comment">// 0x00004000 [14]    SM6          (0) </span></div>
<div class="line"><a id="l00256" name="l00256"></a><span class="lineno">  256</span>    <span class="comment">// 0x00002000 [13]    SM5          (0) </span></div>
<div class="line"><a id="l00257" name="l00257"></a><span class="lineno">  257</span>    <span class="comment">// 0x00001000 [12]    SM4          (0) </span></div>
<div class="line"><a id="l00258" name="l00258"></a><span class="lineno">  258</span>    <span class="comment">// 0x00000800 [11]    SM3          (0) </span></div>
<div class="line"><a id="l00259" name="l00259"></a><span class="lineno">  259</span>    <span class="comment">// 0x00000400 [10]    SM2          (0) </span></div>
<div class="line"><a id="l00260" name="l00260"></a><span class="lineno">  260</span>    <span class="comment">// 0x00000200 [9]     SM1          (0) </span></div>
<div class="line"><a id="l00261" name="l00261"></a><span class="lineno">  261</span>    <span class="comment">// 0x00000100 [8]     SM0          (0) </span></div>
<div class="line"><a id="l00262" name="l00262"></a><span class="lineno">  262</span>    <span class="comment">// 0x00000080 [7]     SM3_TXNFULL  (0) </span></div>
<div class="line"><a id="l00263" name="l00263"></a><span class="lineno">  263</span>    <span class="comment">// 0x00000040 [6]     SM2_TXNFULL  (0) </span></div>
<div class="line"><a id="l00264" name="l00264"></a><span class="lineno">  264</span>    <span class="comment">// 0x00000020 [5]     SM1_TXNFULL  (0) </span></div>
<div class="line"><a id="l00265" name="l00265"></a><span class="lineno">  265</span>    <span class="comment">// 0x00000010 [4]     SM0_TXNFULL  (0) </span></div>
<div class="line"><a id="l00266" name="l00266"></a><span class="lineno">  266</span>    <span class="comment">// 0x00000008 [3]     SM3_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00267" name="l00267"></a><span class="lineno">  267</span>    <span class="comment">// 0x00000004 [2]     SM2_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00268" name="l00268"></a><span class="lineno">  268</span>    <span class="comment">// 0x00000002 [1]     SM1_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00269" name="l00269"></a><span class="lineno">  269</span>    <span class="comment">// 0x00000001 [0]     SM0_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00270" name="l00270"></a><span class="lineno">  270</span>    io_ro_32 intr;</div>
<div class="line"><a id="l00271" name="l00271"></a><span class="lineno">  271</span> </div>
<div class="line"><a id="l00272" name="l00272"></a><span class="lineno">  272</span>    <span class="keyword">union </span>{</div>
<div class="line"><a id="l00273" name="l00273"></a><span class="lineno">  273</span>        <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00274" name="l00274"></a><span class="lineno">  274</span>            _REG_(PIO_IRQ0_INTE_OFFSET) <span class="comment">// PIO_IRQ0_INTE</span></div>
<div class="line"><a id="l00275" name="l00275"></a><span class="lineno">  275</span>            <span class="comment">// Interrupt Enable for irq0</span></div>
<div class="line"><a id="l00276" name="l00276"></a><span class="lineno">  276</span>            <span class="comment">// 0x00000800 [11]    SM3          (0) </span></div>
<div class="line"><a id="l00277" name="l00277"></a><span class="lineno">  277</span>            <span class="comment">// 0x00000400 [10]    SM2          (0) </span></div>
<div class="line"><a id="l00278" name="l00278"></a><span class="lineno">  278</span>            <span class="comment">// 0x00000200 [9]     SM1          (0) </span></div>
<div class="line"><a id="l00279" name="l00279"></a><span class="lineno">  279</span>            <span class="comment">// 0x00000100 [8]     SM0          (0) </span></div>
<div class="line"><a id="l00280" name="l00280"></a><span class="lineno">  280</span>            <span class="comment">// 0x00000080 [7]     SM3_TXNFULL  (0) </span></div>
<div class="line"><a id="l00281" name="l00281"></a><span class="lineno">  281</span>            <span class="comment">// 0x00000040 [6]     SM2_TXNFULL  (0) </span></div>
<div class="line"><a id="l00282" name="l00282"></a><span class="lineno">  282</span>            <span class="comment">// 0x00000020 [5]     SM1_TXNFULL  (0) </span></div>
<div class="line"><a id="l00283" name="l00283"></a><span class="lineno">  283</span>            <span class="comment">// 0x00000010 [4]     SM0_TXNFULL  (0) </span></div>
<div class="line"><a id="l00284" name="l00284"></a><span class="lineno">  284</span>            <span class="comment">// 0x00000008 [3]     SM3_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00285" name="l00285"></a><span class="lineno">  285</span>            <span class="comment">// 0x00000004 [2]     SM2_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00286" name="l00286"></a><span class="lineno">  286</span>            <span class="comment">// 0x00000002 [1]     SM1_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00287" name="l00287"></a><span class="lineno">  287</span>            <span class="comment">// 0x00000001 [0]     SM0_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00288" name="l00288"></a><span class="lineno">  288</span>            io_rw_32 inte0;</div>
<div class="line"><a id="l00289" name="l00289"></a><span class="lineno">  289</span> </div>
<div class="line"><a id="l00290" name="l00290"></a><span class="lineno">  290</span>            _REG_(PIO_IRQ0_INTF_OFFSET) <span class="comment">// PIO_IRQ0_INTF</span></div>
<div class="line"><a id="l00291" name="l00291"></a><span class="lineno">  291</span>            <span class="comment">// Interrupt Force for irq0</span></div>
<div class="line"><a id="l00292" name="l00292"></a><span class="lineno">  292</span>            <span class="comment">// 0x00000800 [11]    SM3          (0) </span></div>
<div class="line"><a id="l00293" name="l00293"></a><span class="lineno">  293</span>            <span class="comment">// 0x00000400 [10]    SM2          (0) </span></div>
<div class="line"><a id="l00294" name="l00294"></a><span class="lineno">  294</span>            <span class="comment">// 0x00000200 [9]     SM1          (0) </span></div>
<div class="line"><a id="l00295" name="l00295"></a><span class="lineno">  295</span>            <span class="comment">// 0x00000100 [8]     SM0          (0) </span></div>
<div class="line"><a id="l00296" name="l00296"></a><span class="lineno">  296</span>            <span class="comment">// 0x00000080 [7]     SM3_TXNFULL  (0) </span></div>
<div class="line"><a id="l00297" name="l00297"></a><span class="lineno">  297</span>            <span class="comment">// 0x00000040 [6]     SM2_TXNFULL  (0) </span></div>
<div class="line"><a id="l00298" name="l00298"></a><span class="lineno">  298</span>            <span class="comment">// 0x00000020 [5]     SM1_TXNFULL  (0) </span></div>
<div class="line"><a id="l00299" name="l00299"></a><span class="lineno">  299</span>            <span class="comment">// 0x00000010 [4]     SM0_TXNFULL  (0) </span></div>
<div class="line"><a id="l00300" name="l00300"></a><span class="lineno">  300</span>            <span class="comment">// 0x00000008 [3]     SM3_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00301" name="l00301"></a><span class="lineno">  301</span>            <span class="comment">// 0x00000004 [2]     SM2_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00302" name="l00302"></a><span class="lineno">  302</span>            <span class="comment">// 0x00000002 [1]     SM1_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00303" name="l00303"></a><span class="lineno">  303</span>            <span class="comment">// 0x00000001 [0]     SM0_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00304" name="l00304"></a><span class="lineno">  304</span>            io_rw_32 intf0;</div>
<div class="line"><a id="l00305" name="l00305"></a><span class="lineno">  305</span> </div>
<div class="line"><a id="l00306" name="l00306"></a><span class="lineno">  306</span>            _REG_(PIO_IRQ0_INTS_OFFSET) <span class="comment">// PIO_IRQ0_INTS</span></div>
<div class="line"><a id="l00307" name="l00307"></a><span class="lineno">  307</span>            <span class="comment">// Interrupt status after masking &amp; forcing for irq0</span></div>
<div class="line"><a id="l00308" name="l00308"></a><span class="lineno">  308</span>            <span class="comment">// 0x00000800 [11]    SM3          (0) </span></div>
<div class="line"><a id="l00309" name="l00309"></a><span class="lineno">  309</span>            <span class="comment">// 0x00000400 [10]    SM2          (0) </span></div>
<div class="line"><a id="l00310" name="l00310"></a><span class="lineno">  310</span>            <span class="comment">// 0x00000200 [9]     SM1          (0) </span></div>
<div class="line"><a id="l00311" name="l00311"></a><span class="lineno">  311</span>            <span class="comment">// 0x00000100 [8]     SM0          (0) </span></div>
<div class="line"><a id="l00312" name="l00312"></a><span class="lineno">  312</span>            <span class="comment">// 0x00000080 [7]     SM3_TXNFULL  (0) </span></div>
<div class="line"><a id="l00313" name="l00313"></a><span class="lineno">  313</span>            <span class="comment">// 0x00000040 [6]     SM2_TXNFULL  (0) </span></div>
<div class="line"><a id="l00314" name="l00314"></a><span class="lineno">  314</span>            <span class="comment">// 0x00000020 [5]     SM1_TXNFULL  (0) </span></div>
<div class="line"><a id="l00315" name="l00315"></a><span class="lineno">  315</span>            <span class="comment">// 0x00000010 [4]     SM0_TXNFULL  (0) </span></div>
<div class="line"><a id="l00316" name="l00316"></a><span class="lineno">  316</span>            <span class="comment">// 0x00000008 [3]     SM3_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00317" name="l00317"></a><span class="lineno">  317</span>            <span class="comment">// 0x00000004 [2]     SM2_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00318" name="l00318"></a><span class="lineno">  318</span>            <span class="comment">// 0x00000002 [1]     SM1_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00319" name="l00319"></a><span class="lineno">  319</span>            <span class="comment">// 0x00000001 [0]     SM0_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00320" name="l00320"></a><span class="lineno">  320</span>            io_ro_32 ints0;</div>
<div class="line"><a id="l00321" name="l00321"></a><span class="lineno">  321</span> </div>
<div class="line"><a id="l00322" name="l00322"></a><span class="lineno">  322</span>            _REG_(PIO_IRQ1_INTE_OFFSET) <span class="comment">// PIO_IRQ1_INTE</span></div>
<div class="line"><a id="l00323" name="l00323"></a><span class="lineno">  323</span>            <span class="comment">// Interrupt Enable for irq1</span></div>
<div class="line"><a id="l00324" name="l00324"></a><span class="lineno">  324</span>            <span class="comment">// 0x00000800 [11]    SM3          (0) </span></div>
<div class="line"><a id="l00325" name="l00325"></a><span class="lineno">  325</span>            <span class="comment">// 0x00000400 [10]    SM2          (0) </span></div>
<div class="line"><a id="l00326" name="l00326"></a><span class="lineno">  326</span>            <span class="comment">// 0x00000200 [9]     SM1          (0) </span></div>
<div class="line"><a id="l00327" name="l00327"></a><span class="lineno">  327</span>            <span class="comment">// 0x00000100 [8]     SM0          (0) </span></div>
<div class="line"><a id="l00328" name="l00328"></a><span class="lineno">  328</span>            <span class="comment">// 0x00000080 [7]     SM3_TXNFULL  (0) </span></div>
<div class="line"><a id="l00329" name="l00329"></a><span class="lineno">  329</span>            <span class="comment">// 0x00000040 [6]     SM2_TXNFULL  (0) </span></div>
<div class="line"><a id="l00330" name="l00330"></a><span class="lineno">  330</span>            <span class="comment">// 0x00000020 [5]     SM1_TXNFULL  (0) </span></div>
<div class="line"><a id="l00331" name="l00331"></a><span class="lineno">  331</span>            <span class="comment">// 0x00000010 [4]     SM0_TXNFULL  (0) </span></div>
<div class="line"><a id="l00332" name="l00332"></a><span class="lineno">  332</span>            <span class="comment">// 0x00000008 [3]     SM3_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00333" name="l00333"></a><span class="lineno">  333</span>            <span class="comment">// 0x00000004 [2]     SM2_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00334" name="l00334"></a><span class="lineno">  334</span>            <span class="comment">// 0x00000002 [1]     SM1_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00335" name="l00335"></a><span class="lineno">  335</span>            <span class="comment">// 0x00000001 [0]     SM0_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00336" name="l00336"></a><span class="lineno">  336</span>            io_rw_32 inte1;</div>
<div class="line"><a id="l00337" name="l00337"></a><span class="lineno">  337</span> </div>
<div class="line"><a id="l00338" name="l00338"></a><span class="lineno">  338</span>            _REG_(PIO_IRQ1_INTF_OFFSET) <span class="comment">// PIO_IRQ1_INTF</span></div>
<div class="line"><a id="l00339" name="l00339"></a><span class="lineno">  339</span>            <span class="comment">// Interrupt Force for irq1</span></div>
<div class="line"><a id="l00340" name="l00340"></a><span class="lineno">  340</span>            <span class="comment">// 0x00000800 [11]    SM3          (0) </span></div>
<div class="line"><a id="l00341" name="l00341"></a><span class="lineno">  341</span>            <span class="comment">// 0x00000400 [10]    SM2          (0) </span></div>
<div class="line"><a id="l00342" name="l00342"></a><span class="lineno">  342</span>            <span class="comment">// 0x00000200 [9]     SM1          (0) </span></div>
<div class="line"><a id="l00343" name="l00343"></a><span class="lineno">  343</span>            <span class="comment">// 0x00000100 [8]     SM0          (0) </span></div>
<div class="line"><a id="l00344" name="l00344"></a><span class="lineno">  344</span>            <span class="comment">// 0x00000080 [7]     SM3_TXNFULL  (0) </span></div>
<div class="line"><a id="l00345" name="l00345"></a><span class="lineno">  345</span>            <span class="comment">// 0x00000040 [6]     SM2_TXNFULL  (0) </span></div>
<div class="line"><a id="l00346" name="l00346"></a><span class="lineno">  346</span>            <span class="comment">// 0x00000020 [5]     SM1_TXNFULL  (0) </span></div>
<div class="line"><a id="l00347" name="l00347"></a><span class="lineno">  347</span>            <span class="comment">// 0x00000010 [4]     SM0_TXNFULL  (0) </span></div>
<div class="line"><a id="l00348" name="l00348"></a><span class="lineno">  348</span>            <span class="comment">// 0x00000008 [3]     SM3_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00349" name="l00349"></a><span class="lineno">  349</span>            <span class="comment">// 0x00000004 [2]     SM2_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00350" name="l00350"></a><span class="lineno">  350</span>            <span class="comment">// 0x00000002 [1]     SM1_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00351" name="l00351"></a><span class="lineno">  351</span>            <span class="comment">// 0x00000001 [0]     SM0_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00352" name="l00352"></a><span class="lineno">  352</span>            io_rw_32 intf1;</div>
<div class="line"><a id="l00353" name="l00353"></a><span class="lineno">  353</span> </div>
<div class="line"><a id="l00354" name="l00354"></a><span class="lineno">  354</span>            _REG_(PIO_IRQ1_INTS_OFFSET) <span class="comment">// PIO_IRQ1_INTS</span></div>
<div class="line"><a id="l00355" name="l00355"></a><span class="lineno">  355</span>            <span class="comment">// Interrupt status after masking &amp; forcing for irq1</span></div>
<div class="line"><a id="l00356" name="l00356"></a><span class="lineno">  356</span>            <span class="comment">// 0x00000800 [11]    SM3          (0) </span></div>
<div class="line"><a id="l00357" name="l00357"></a><span class="lineno">  357</span>            <span class="comment">// 0x00000400 [10]    SM2          (0) </span></div>
<div class="line"><a id="l00358" name="l00358"></a><span class="lineno">  358</span>            <span class="comment">// 0x00000200 [9]     SM1          (0) </span></div>
<div class="line"><a id="l00359" name="l00359"></a><span class="lineno">  359</span>            <span class="comment">// 0x00000100 [8]     SM0          (0) </span></div>
<div class="line"><a id="l00360" name="l00360"></a><span class="lineno">  360</span>            <span class="comment">// 0x00000080 [7]     SM3_TXNFULL  (0) </span></div>
<div class="line"><a id="l00361" name="l00361"></a><span class="lineno">  361</span>            <span class="comment">// 0x00000040 [6]     SM2_TXNFULL  (0) </span></div>
<div class="line"><a id="l00362" name="l00362"></a><span class="lineno">  362</span>            <span class="comment">// 0x00000020 [5]     SM1_TXNFULL  (0) </span></div>
<div class="line"><a id="l00363" name="l00363"></a><span class="lineno">  363</span>            <span class="comment">// 0x00000010 [4]     SM0_TXNFULL  (0) </span></div>
<div class="line"><a id="l00364" name="l00364"></a><span class="lineno">  364</span>            <span class="comment">// 0x00000008 [3]     SM3_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00365" name="l00365"></a><span class="lineno">  365</span>            <span class="comment">// 0x00000004 [2]     SM2_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00366" name="l00366"></a><span class="lineno">  366</span>            <span class="comment">// 0x00000002 [1]     SM1_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00367" name="l00367"></a><span class="lineno">  367</span>            <span class="comment">// 0x00000001 [0]     SM0_RXNEMPTY (0) </span></div>
<div class="line"><a id="l00368" name="l00368"></a><span class="lineno">  368</span>            io_ro_32 ints1;</div>
<div class="line"><a id="l00369" name="l00369"></a><span class="lineno">  369</span>        };</div>
<div class="line"><a id="l00370" name="l00370"></a><span class="lineno">  370</span>        <a class="code hl_struct" href="structpio__irq__ctrl__hw__t.html">pio_irq_ctrl_hw_t</a> irq_ctrl[2];</div>
<div class="line"><a id="l00371" name="l00371"></a><span class="lineno">  371</span>    };</div>
<div class="line"><a id="l00372" name="l00372"></a><span class="lineno">  372</span>} <a class="code hl_struct" href="structpio__hw__t.html">pio_hw_t</a>;</div>
<div class="line"><a id="l00373" name="l00373"></a><span class="lineno">  373</span> </div>
<div class="line"><a id="l00374" name="l00374"></a><span class="lineno">  374</span><span class="preprocessor">#define pio0_hw ((pio_hw_t *)PIO0_BASE)</span></div>
<div class="line"><a id="l00375" name="l00375"></a><span class="lineno">  375</span><span class="preprocessor">#define pio1_hw ((pio_hw_t *)PIO1_BASE)</span></div>
<div class="line"><a id="l00376" name="l00376"></a><span class="lineno">  376</span><span class="preprocessor">#define pio2_hw ((pio_hw_t *)PIO2_BASE)</span></div>
<div class="line"><a id="l00377" name="l00377"></a><span class="lineno">  377</span><span class="keyword">static_assert</span>(<span class="keyword">sizeof</span> (<a class="code hl_struct" href="structpio__hw__t.html">pio_hw_t</a>) == 0x0188, <span class="stringliteral">&quot;&quot;</span>);</div>
<div class="line"><a id="l00378" name="l00378"></a><span class="lineno">  378</span> </div>
<div class="line"><a id="l00379" name="l00379"></a><span class="lineno">  379</span><span class="preprocessor">#endif </span><span class="comment">// _HARDWARE_STRUCTS_PIO_H</span></div>
<div class="line"><a id="l00380" name="l00380"></a><span class="lineno">  380</span> </div>
<div class="ttc" id="aaddress__mapped_8h_html"><div class="ttname"><a href="address__mapped_8h.html">address_mapped.h</a></div></div>
<div class="ttc" id="astructpio__hw__t_html"><div class="ttname"><a href="structpio__hw__t.html">pio_hw_t</a></div><div class="ttdef"><b>Definition:</b> pio.h:132</div></div>
<div class="ttc" id="astructpio__irq__ctrl__hw__t_html"><div class="ttname"><a href="structpio__irq__ctrl__hw__t.html">pio_irq_ctrl_hw_t</a></div><div class="ttdef"><b>Definition:</b> pio.h:82</div></div>
<div class="ttc" id="astructpio__sm__hw__t_html"><div class="ttname"><a href="structpio__sm__hw__t.html">pio_sm_hw_t</a></div><div class="ttdef"><b>Definition:</b> pio.h:26</div></div>
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